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Ensure only correct packet buffer is double buffer is written to

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This commit is contained in:
Robert Ghilduta 2021-10-04 15:50:10 -07:00
parent 45c79ef635
commit 8d9ffaa81c
1 changed files with 6 additions and 5 deletions
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11
fpga/vhdl/wlan_rx_packet_buffer.vhd
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@ -209,10 +209,12 @@ begin
future.buf_a_reset <= '0' ;
future.buf_b_reset <= '0' ;
future.buf_a_ready <= '0' ;
future.buf_b_ready <= '0' ;
case current.wfsm is
when IDLE =>
if( (framer_quiet_reset = '0' and in_params_valid = '1') or dsss_params_valid = '1' ) then
if( current.buf_a_writing = '1' ) then
if( current.buf_a_writing = '1' and fifo_a_empty = '1') then
if( dsss_params_valid = '1' ) then
future.buf_a_params <= dsss_params ;
@ -220,17 +222,16 @@ begin
future.buf_a_params <= in_params ;
end if ;
future.buf_a_ready <= '0' ;
else
future.wfsm <= WRITE_DATA ;
elsif( current.buf_a_writing = '0' and fifo_b_empty = '1' ) then
if( dsss_params_valid = '1' ) then
future.buf_b_params <= dsss_params ;
else
future.buf_b_params <= in_params ;
end if ;
future.buf_b_ready <= '0' ;
future.wfsm <= WRITE_DATA ;
end if ;
future.dsss_mode <= dsss_params_valid ;
future.wfsm <= WRITE_DATA ;
end if ;
when WRITE_DATA =>