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Change Viterbi decoder core

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This commit replaces the modem's Viterbi decoder core with the one in
bladeRF-wiphy. To use the Altera core instead, revert this commit.
This commit is contained in:
Robert Ghilduta 2021-01-10 21:23:48 -08:00
parent 7b8d5aa163
commit 7a07340675
1 changed files with 38 additions and 13 deletions
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51
fpga/vhdl/wlan_viterbi_decoder.vhd
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@ -84,6 +84,14 @@ architecture arch of wlan_viterbi_decoder is
signal current, future : state_t := NULL_STATE ;
function fix_var( x : signed(7 downto 0) ) return std_logic_vector is
variable ret : std_logic_vector(7 downto 0);
begin
ret(6 downto 0) := not(std_logic_vector(x(6 downto 0)));
ret(7) := x(7);
return (ret);
end function;
begin
done <= current.done ;
@ -131,21 +139,38 @@ begin
rr <= std_logic_vector(in_soft_a) & std_logic_vector(in_soft_b) ;
sink_val <= in_valid ;
U_altera_decoder : entity viterbi_decoder.viterbi_decoder
port map (
clk => clock,
reset => core_reset,
--U_altera_decoder : entity viterbi_decoder.viterbi_decoder
-- port map (
-- clk => clock,
-- reset => core_reset,
-- sink_val => sink_val,
-- sink_rdy => sink_rdy,
-- rr => rr,
-- eras_sym => in_erasure,
-- source_rdy => source_rdy,
-- source_val => source_val,
-- decbit => decbit,
-- normalizations => normalizations
-- ) ;
U_vit : entity work.viterbi_decoder
generic map(
TB_LEN => 60
)
port map(
clock => clock,
reset => core_reset,
in_a => (fix_var(in_soft_a)),
in_b => (fix_var(in_soft_b)),
erasure => in_erasure(0) & in_erasure(1),
bsd_valid => in_valid,
out_bit => decbit,
out_valid => source_val
);
sink_val => sink_val,
sink_rdy => sink_rdy,
rr => rr,
eras_sym => in_erasure,
source_rdy => source_rdy,
source_val => source_val,
decbit => decbit,
normalizations => normalizations
) ;
out_dec_bit <= decbit ;
out_dec_valid <= source_val ;