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Add cores
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Nuand
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93
fpga/ip/altera/fft64/fft64.qsys
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93
fpga/ip/altera/fft64/fft64.qsys
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element fft_ii_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="deviceSpeedGrade" value="8" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="false" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VHDL" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="clk" internal="fft_ii_0.clk" type="clock" dir="end">
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<port name="clk" internal="clk" />
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</interface>
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<interface name="rst" internal="fft_ii_0.rst" type="reset" dir="end">
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<port name="reset_n" internal="reset_n" />
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</interface>
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<interface name="sink" internal="fft_ii_0.sink" type="conduit" dir="end">
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<port name="sink_valid" internal="sink_valid" />
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<port name="sink_ready" internal="sink_ready" />
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<port name="sink_error" internal="sink_error" />
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<port name="sink_sop" internal="sink_sop" />
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<port name="sink_eop" internal="sink_eop" />
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<port name="sink_real" internal="sink_real" />
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<port name="sink_imag" internal="sink_imag" />
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<port name="fftpts_in" internal="fftpts_in" />
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<port name="inverse" internal="inverse" />
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</interface>
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<interface name="source" internal="fft_ii_0.source" type="conduit" dir="end">
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<port name="source_valid" internal="source_valid" />
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<port name="source_ready" internal="source_ready" />
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<port name="source_error" internal="source_error" />
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<port name="source_sop" internal="source_sop" />
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<port name="source_eop" internal="source_eop" />
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<port name="source_real" internal="source_real" />
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<port name="source_imag" internal="source_imag" />
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<port name="fftpts_out" internal="fftpts_out" />
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</interface>
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<module
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name="fft_ii_0"
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kind="altera_fft_ii"
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version="19.1"
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enabled="1"
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autoexport="1">
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<parameter name="data_flow" value="Variable Streaming" />
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<parameter name="data_rep" value="Fixed Point" />
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<parameter name="design_env" value="NATIVE" />
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<parameter name="direction" value="Bi-directional" />
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<parameter name="dsp_resource_opt" value="false" />
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<parameter name="engine_arch" value="Quad Output" />
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<parameter name="hard_fp" value="false" />
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<parameter name="hyper_opt" value="false" />
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<parameter name="in_order" value="Natural" />
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<parameter name="in_width" value="16" />
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<parameter name="length" value="64" />
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<parameter name="num_engines" value="1" />
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<parameter name="out_order" value="Natural" />
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<parameter name="out_width" value="23" />
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<parameter name="selected_device_family" value="Cyclone V" />
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<parameter name="twid_width" value="24" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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1
fpga/ip/altera/fft64/generate.sh
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1
fpga/ip/altera/fft64/generate.sh
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qsys-generate --sim --synthesis=VHDL ./fft64.qsys
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1
fpga/ip/altera/viterbi_decoder/generate.sh
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1
fpga/ip/altera/viterbi_decoder/generate.sh
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qsys-generate --sim --synthesis=VHDL viterbi_decoder.qsys
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91
fpga/ip/altera/viterbi_decoder/viterbi_decoder.qsys
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91
fpga/ip/altera/viterbi_decoder/viterbi_decoder.qsys
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<?xml version="1.0" encoding="UTF-8"?>
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<system name="$${FILENAME}">
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<component
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name="$${FILENAME}"
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displayName="$${FILENAME}"
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version="1.0"
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description=""
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tags="INTERNAL_COMPONENT=true"
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categories="System" />
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<parameter name="bonusData"><![CDATA[bonusData
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{
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element viterbi_ii_0
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{
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datum _sortIndex
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{
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value = "0";
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type = "int";
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}
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}
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}
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]]></parameter>
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<parameter name="clockCrossingAdapter" value="HANDSHAKE" />
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<parameter name="deviceSpeedGrade" value="8" />
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<parameter name="fabricMode" value="QSYS" />
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<parameter name="generateLegacySim" value="true" />
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<parameter name="generationId" value="0" />
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<parameter name="globalResetBus" value="false" />
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<parameter name="hdlLanguage" value="VHDL" />
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<parameter name="hideFromIPCatalog" value="true" />
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<parameter name="lockedInterfaceDefinition" value="" />
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<parameter name="maxAdditionalLatency" value="1" />
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<parameter name="projectName" value="" />
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<parameter name="sopcBorderPoints" value="false" />
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<parameter name="systemHash" value="0" />
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<parameter name="testBenchDutName" value="" />
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<parameter name="timeStamp" value="0" />
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<parameter name="useTestBenchNamingPattern" value="false" />
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<instanceScript></instanceScript>
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<interface name="clk" internal="viterbi_ii_0.clk" type="clock" dir="end">
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<port name="clk" internal="clk" />
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</interface>
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<interface name="in" internal="viterbi_ii_0.in" type="conduit" dir="end">
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<port name="sink_val" internal="sink_val" />
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<port name="sink_rdy" internal="sink_rdy" />
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<port name="eras_sym" internal="eras_sym" />
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<port name="rr" internal="rr" />
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</interface>
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<interface name="out" internal="viterbi_ii_0.out" type="conduit" dir="end">
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<port name="source_val" internal="source_val" />
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<port name="source_rdy" internal="source_rdy" />
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<port name="normalizations" internal="normalizations" />
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<port name="decbit" internal="decbit" />
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</interface>
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<interface name="rst" internal="viterbi_ii_0.rst" type="reset" dir="end">
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<port name="reset" internal="reset" />
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</interface>
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<module
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name="viterbi_ii_0"
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kind="altera_viterbi_ii"
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version="19.1"
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enabled="1"
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autoexport="1">
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<parameter name="BSF" value="1" />
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<parameter name="FMAX" value="80.0" />
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<parameter name="ISBER" value="0" />
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<parameter name="ISOCTAL" value="Decimal" />
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<parameter name="L" value="7" />
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<parameter name="NODESYNC" value="0" />
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<parameter name="acs_units" value="1" />
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<parameter name="dec_mode" value="V" />
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<parameter name="design_env" value="NATIVE" />
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<parameter name="ga" value="91" />
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<parameter name="gb" value="121" />
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<parameter name="gc" value="0" />
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<parameter name="gd" value="0" />
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<parameter name="ge" value="0" />
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<parameter name="gf" value="0" />
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<parameter name="gg" value="0" />
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<parameter name="n" value="2" />
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<parameter name="ncodes" value="1" />
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<parameter name="parallel_optimization" value="Continuous" />
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<parameter name="selected_device_family" value="Cyclone V" />
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<parameter name="softbits" value="8" />
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<parameter name="v" value="42" />
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<parameter name="viterbi_type" value="Parallel" />
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</module>
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<interconnectRequirement for="$system" name="qsys_mm.clockCrossingAdapter" value="HANDSHAKE" />
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<interconnectRequirement for="$system" name="qsys_mm.enableEccProtection" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.insertDefaultSlave" value="FALSE" />
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<interconnectRequirement for="$system" name="qsys_mm.maxAdditionalLatency" value="1" />
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</system>
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5
fpga/ip/altera/wlan_pll/generate.sh
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5
fpga/ip/altera/wlan_pll/generate.sh
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ip-generate --file-set=QUARTUS_SYNTH --component-name=altera_pll --output-name=wlan_pll \
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--component-param=gui_reference_clock_frequency="40MHz" \
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--component-param=gui_output_clock_frequency0="80MHz" \
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--component-param=gui_phase_shift0="0ps" \
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--component-param=gui_duty_cycle0="50%"
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1
fpga/ip/generate.sh
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1
fpga/ip/generate.sh
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for i in */*/generate.sh; do echo "Running $i"; (cd `dirname $i`; sh generate.sh); done
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