mirror of
https://github.com/Nuand/bladeRF-wiphy.git
synced 2024-12-18 21:28:06 +00:00
299 lines
11 KiB
VHDL
299 lines
11 KiB
VHDL
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-- This file is part of bladeRF-wiphy.
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--
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-- Copyright (C) 2020 Nuand, LLC.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License along
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-- with this program; if not, write to the Free Software Foundation, Inc.,
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-- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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library ieee ;
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use ieee.std_logic_1164.all ;
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use ieee.numeric_std.all ;
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use ieee.math_real.all ;
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entity wlan_agc_drv is
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port (
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-- 80 MHz clock and async asserted, sync deasserted reset
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clock : in std_logic ;
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reset : in std_logic ;
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enable : in std_logic ;
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gain_inc_req : in std_logic ;
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gain_dec_req : in std_logic ;
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gain_rst_req : in std_logic ;
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gain_ack : out std_logic ;
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gain_nack : out std_logic ;
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gain_high : out std_logic ;
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gain_mid : out std_logic ;
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gain_low : out std_logic ;
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-- Arbiter
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arbiter_req : out std_logic ;
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arbiter_grant : in std_logic ;
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arbiter_done : out std_logic ;
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-- Misc
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band_sel : in std_logic ;
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-- Physical Interface
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sclk : out std_logic ;
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miso : in std_logic ;
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mosi : out std_logic ;
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cs_n : out std_logic
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) ;
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end entity ;
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architecture arch of wlan_agc_drv is
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type gain_state_t is ( UNSET_GAIN_STATE, HIGH_GAIN_STATE, MID_GAIN_STATE, LOW_GAIN_STATE ) ;
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type lna_gain_t is ( LNA_MID_GAIN, LNA_MAX_GAIN ) ;
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type rxvga1_gain_t is ( RXVGA1_MID_GAIN, RXVGA1_MAX_GAIN ) ;
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type rxvga2_gain_t is ( RXVGA2_LOW_GAIN, RXVGA2_MID_GAIN ) ;
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type fsm_t is ( INIT, IDLE, SPI_WRITE, SPI_WRITE_GRANTED, WRITE_RXVGA1, WRITE_RXVGA2,
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UPDATE_GAINS, SPI_WAIT, SPI_WAIT_1 ) ;
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type gain_t is record
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lna_gain : lna_gain_t ;
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rxvga1_gain : rxvga1_gain_t ;
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rxvga2_gain : rxvga2_gain_t ;
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end record ;
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-- -82dBm - -52dBm
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constant HIGH_GAIN : gain_t := (
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lna_gain => LNA_MAX_GAIN, -- 6 dB (Max)
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rxvga1_gain => RXVGA1_MAX_GAIN, -- 30 dB
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rxvga2_gain => RXVGA2_MID_GAIN -- 15 dB
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) ;
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-- -52dBm - -30dBm
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constant MID_GAIN : gain_t := (
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lna_gain => LNA_MID_GAIN, -- 3 dB (Mid)
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rxvga1_gain => RXVGA1_MAX_GAIN, -- 30 dB
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rxvga2_gain => RXVGA2_LOW_GAIN -- 0 dB
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) ;
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-- -30dBm - -17dBm
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constant LOW_GAIN : gain_t := (
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lna_gain => LNA_MID_GAIN, -- 3 dB (Mid)
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rxvga1_gain => RXVGA1_MID_GAIN, -- 12 dB
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rxvga2_gain => RXVGA2_LOW_GAIN -- 0 dB
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) ;
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type state_t is record
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fsm : fsm_t ;
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nfsm : fsm_t ;
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initializing : std_logic ;
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ack : std_logic ;
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nack : std_logic ;
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gain_state : gain_state_t ;
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current_gain : gain_t ;
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future_gain : gain_t ;
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arbiter_req : std_logic ;
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arbiter_done : std_logic ;
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gain_inc_req : std_logic ;
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gain_dec_req : std_logic ;
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gain_rst_req : std_logic ;
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-- Avalon-MM Interface
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mm_write : std_logic ;
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mm_addr : std_logic_vector(7 downto 0) ;
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mm_din : std_logic_vector(7 downto 0) ;
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end record ;
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function NULL_STATE return state_t is
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variable rv : state_t ;
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begin
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rv.fsm := INIT ;
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rv.nfsm := INIT ;
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rv.initializing := '0' ;
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rv.arbiter_req := '0' ;
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rv.arbiter_done := '0' ;
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rv.gain_inc_req := '0' ;
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rv.gain_dec_req := '0' ;
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rv.gain_rst_req := '0' ;
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rv.gain_state := UNSET_GAIN_STATE ;
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rv.mm_addr := ( others => '0' ) ;
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rv.mm_din := ( others => '0' ) ;
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return rv ;
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end function ;
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signal current, future : state_t := NULL_STATE ;
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signal mm_busy : std_logic ;
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begin
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arbiter_req <= current.arbiter_req ;
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arbiter_done <= current.arbiter_done ;
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gain_high <= '1' when current.gain_state = HIGH_GAIN_STATE else '0' ;
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gain_mid <= '1' when current.gain_state = MID_GAIN_STATE else '0' ;
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gain_low <= '1' when current.gain_state = LOW_GAIN_STATE else '0' ;
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gain_ack <= current.ack ; --'1' when current.fsm = UPDATE_GAINS else '0' ;
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gain_nack <= current.nack ;
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sync : process(clock, reset)
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begin
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if( reset = '1' ) then
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current <= NULL_STATE ;
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elsif( rising_edge(clock) ) then
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current <= future ;
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end if ;
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end process ;
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comb : process(all)
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begin
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future <= current ;
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future.mm_write <= '0' ;
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future.ack <= '0' ;
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future.nack <= '0' ;
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future.arbiter_done <= '0' ;
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future.arbiter_req <= '0' ;
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future.gain_inc_req <= gain_inc_req ;
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future.gain_dec_req <= gain_dec_req ;
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future.gain_rst_req <= gain_rst_req ;
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case current.fsm is
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when INIT =>
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future.nack <= '1' ;
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if( enable = '1' ) then
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future.nack <= '0' ;
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future.gain_state <= HIGH_GAIN_STATE ;
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future.future_gain <= HIGH_GAIN ;
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future.initializing <= '1' ;
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future.fsm <= SPI_WRITE ;
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end if ;
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when IDLE =>
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if( current.gain_inc_req = '1' ) then
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if( current.gain_state = LOW_GAIN_STATE ) then
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future.gain_state <= MID_GAIN_STATE ;
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future.future_gain <= MID_GAIN ;
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future.fsm <= SPI_WRITE ;
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elsif( current.gain_state = MID_GAIN_STATE ) then
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future.gain_state <= HIGH_GAIN_STATE ;
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future.future_gain <= HIGH_GAIN ;
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future.fsm <= SPI_WRITE ;
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else
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future.nack <= '1' ;
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-- we are already as high as can be
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end if ;
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end if ;
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if( current.gain_dec_req = '1' ) then
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if( current.gain_state = MID_GAIN_STATE ) then
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future.gain_state <= LOW_GAIN_STATE ;
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future.future_gain <= LOW_GAIN ;
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future.fsm <= SPI_WRITE ;
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elsif( current.gain_state = HIGH_GAIN_STATE ) then
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future.gain_state <= MID_GAIN_STATE ;
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future.future_gain <= MID_GAIN ;
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future.fsm <= SPI_WRITE ;
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else
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future.nack <= '1' ;
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-- we are already as low as can be
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end if ;
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end if ;
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if( current.gain_rst_req = '1' ) then
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future.gain_state <= HIGH_GAIN_STATE ;
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future.future_gain <= HIGH_GAIN ;
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end if ;
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if( enable = '0' ) then
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future.fsm <= INIT ;
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end if ;
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when SPI_WRITE =>
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future.arbiter_req <= '1' ;
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if( arbiter_grant = '1' ) then
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future.fsm <= SPI_WRITE_GRANTED ;
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end if ;
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when SPI_WRITE_GRANTED =>
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if( current.current_gain.lna_gain /= current.future_gain.lna_gain or
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current.initializing = '1' ) then
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future.mm_addr <= x"75" ;
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if (current.future_gain.lna_gain = LNA_MAX_GAIN ) then
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if (band_sel = '0' ) then
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future.mm_din <= x"D0";
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else
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future.mm_din <= x"E0";
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end if ;
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elsif (current.future_gain.lna_gain = LNA_MID_GAIN ) then
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if (band_sel = '0' ) then
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future.mm_din <= x"90";
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else
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future.mm_din <= x"A0";
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end if ;
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end if ;
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future.mm_write <= '1' ;
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future.fsm <= SPI_WAIT ;
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future.nfsm <= WRITE_RXVGA1 ;
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else
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future.fsm <= WRITE_RXVGA1 ;
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end if ;
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when WRITE_RXVGA1 =>
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if( current.current_gain.rxvga1_gain /= current.future_gain.rxvga1_gain or
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current.initializing = '1' ) then
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future.mm_addr <= x"76" ;
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if (current.future_gain.rxvga1_gain = RXVGA1_MAX_GAIN ) then
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future.mm_din <= x"78" ;
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elsif (current.future_gain.rxvga1_gain = RXVGA1_MID_GAIN ) then
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future.mm_din <= x"46" ;
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end if ;
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future.mm_write <= '1' ;
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future.fsm <= SPI_WAIT ;
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future.nfsm <= WRITE_RXVGA2 ;
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else
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future.fsm <= WRITE_RXVGA2 ;
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end if ;
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when WRITE_RXVGA2 =>
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if( current.current_gain.rxvga2_gain /= current.future_gain.rxvga2_gain or
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current.initializing = '1' ) then
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future.mm_addr <= x"65" ;
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if (current.future_gain.rxvga2_gain = RXVGA2_MID_GAIN ) then
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future.mm_din <= x"05" ;
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elsif (current.future_gain.rxvga2_gain = RXVGA2_LOW_GAIN ) then
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future.mm_din <= x"00" ;
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end if ;
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future.mm_write <= '1' ;
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future.fsm <= SPI_WAIT ;
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future.nfsm <= UPDATE_GAINS ;
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else
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future.fsm <= UPDATE_GAINS ;
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end if ;
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when UPDATE_GAINS =>
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future.ack <= '1' ;
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future.initializing <= '0' ;
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future.current_gain <= current.future_gain ;
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future.arbiter_done <= '1' ;
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future.fsm <= IDLE ;
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when SPI_WAIT =>
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future.fsm <= SPI_WAIT_1 ;
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when SPI_WAIT_1 =>
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if( mm_busy = '0' ) then
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future.fsm <= current.nfsm ;
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end if ;
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end case ;
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end process ;
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end architecture ;
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