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https://github.com/balena-os/balena-supervisor.git
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89 lines
3.1 KiB
Diff
89 lines
3.1 KiB
Diff
commit 03def348bdd766df0c508ee8cbf6ceba00e8d78c
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Author: Pablo Carranza Velez <pablo@resin.io>
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Date: Fri Jun 9 15:07:55 2017 -0700
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Implement atomic quadword ops with FILD/FISTP
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Adapted from https://github.com/resin-io/resin-supervisor/blob/c7a7ba93fb46775006f0739ced41fc0a2059b426/gosuper/go-1.6.3-patches/0002-implement-atomic-quadword-ops-with-FILD-FISTP.patch
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Original author: Petros Angelatos <petrosagg@gmail.com>
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Signed-off-by: Pablo Carranza Velez <pablo@resin.io>
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diff --git a/src/runtime/internal/atomic/asm_386.s b/src/runtime/internal/atomic/asm_386.s
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index 882906e..d37c675 100644
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--- a/src/runtime/internal/atomic/asm_386.s
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+++ b/src/runtime/internal/atomic/asm_386.s
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@@ -124,12 +124,10 @@ TEXT runtime∕internal∕atomic·Load64(SB), NOSPLIT, $0-12
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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LEAL ret_lo+4(FP), BX
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0(%EBX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x03
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ (%EBX)
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+ BYTE $0xdf; BYTE $0x3b
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RET
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// void runtime∕internal∕atomic·Store64(uint64 volatile* addr, uint64 v);
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@@ -138,13 +136,10 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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MOVL $0, AX
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diff --git a/src/sync/atomic/asm_386.s b/src/sync/atomic/asm_386.s
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index f2a13da..c7787a4 100644
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--- a/src/sync/atomic/asm_386.s
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+++ b/src/sync/atomic/asm_386.s
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@@ -157,12 +157,10 @@ TEXT ·LoadUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0x8(%ESP)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- EMMS
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x7c; BYTE $0x24; BYTE $0x08
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RET
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TEXT ·LoadUintptr(SB),NOSPLIT,$0-8
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@@ -188,12 +186,10 @@ TEXT ·StoreUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- EMMS
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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XORL AX, AX
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