commit 03def348bdd766df0c508ee8cbf6ceba00e8d78c
Author: Pablo Carranza Velez <pablo@resin.io>
Date:   Fri Jun 9 15:07:55 2017 -0700

    Implement atomic quadword ops with FILD/FISTP
    
    Adapted from https://github.com/resin-io/resin-supervisor/blob/c7a7ba93fb46775006f0739ced41fc0a2059b426/gosuper/go-1.6.3-patches/0002-implement-atomic-quadword-ops-with-FILD-FISTP.patch
    Original author: Petros Angelatos <petrosagg@gmail.com>
    
    Signed-off-by: Pablo Carranza Velez <pablo@resin.io>

diff --git a/src/runtime/internal/atomic/asm_386.s b/src/runtime/internal/atomic/asm_386.s
index 882906e..d37c675 100644
--- a/src/runtime/internal/atomic/asm_386.s
+++ b/src/runtime/internal/atomic/asm_386.s
@@ -124,12 +124,10 @@ TEXT runtime∕internal∕atomic·Load64(SB), NOSPLIT, $0-12
 	JZ	2(PC)
 	MOVL	0, AX // crash with nil ptr deref
 	LEAL	ret_lo+4(FP), BX
-	// MOVQ (%EAX), %MM0
-	BYTE $0x0f; BYTE $0x6f; BYTE $0x00
-	// MOVQ %MM0, 0(%EBX)
-	BYTE $0x0f; BYTE $0x7f; BYTE $0x03
-	// EMMS
-	BYTE $0x0F; BYTE $0x77
+	// FILDQ (%EAX)
+	BYTE $0xdf; BYTE $0x28
+	// FISTPQ (%EBX)
+	BYTE $0xdf; BYTE $0x3b
 	RET
 
 // void runtime∕internal∕atomic·Store64(uint64 volatile* addr, uint64 v);
@@ -138,13 +136,10 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-12
 	TESTL	$7, AX
 	JZ	2(PC)
 	MOVL	0, AX // crash with nil ptr deref
-	// MOVQ and EMMS were introduced on the Pentium MMX.
-	// MOVQ 0x8(%ESP), %MM0
-	BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
-	// MOVQ %MM0, (%EAX)
-	BYTE $0x0f; BYTE $0x7f; BYTE $0x00 
-	// EMMS
-	BYTE $0x0F; BYTE $0x77
+	// FILDQ 0x8(%ESP)
+	BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
+	// FISTPQ (%EAX)
+	BYTE $0xdf; BYTE $0x38
 	// This is essentially a no-op, but it provides required memory fencing.
 	// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
 	MOVL	$0, AX
diff --git a/src/sync/atomic/asm_386.s b/src/sync/atomic/asm_386.s
index f2a13da..c7787a4 100644
--- a/src/sync/atomic/asm_386.s
+++ b/src/sync/atomic/asm_386.s
@@ -157,12 +157,10 @@ TEXT ·LoadUint64(SB),NOSPLIT,$0-12
 	TESTL	$7, AX
 	JZ	2(PC)
 	MOVL	0, AX // crash with nil ptr deref
-	// MOVQ and EMMS were introduced on the Pentium MMX.
-	// MOVQ (%EAX), %MM0
-	BYTE $0x0f; BYTE $0x6f; BYTE $0x00
-	// MOVQ %MM0, 0x8(%ESP)
-	BYTE $0x0f; BYTE $0x7f; BYTE $0x44; BYTE $0x24; BYTE $0x08
-	EMMS
+	// FILDQ (%EAX)
+	BYTE $0xdf; BYTE $0x28
+	// FISTPQ 0x8(%ESP)
+	BYTE $0xdf; BYTE $0x7c; BYTE $0x24; BYTE $0x08
 	RET
 
 TEXT ·LoadUintptr(SB),NOSPLIT,$0-8
@@ -188,12 +186,10 @@ TEXT ·StoreUint64(SB),NOSPLIT,$0-12
 	TESTL	$7, AX
 	JZ	2(PC)
 	MOVL	0, AX // crash with nil ptr deref
-	// MOVQ and EMMS were introduced on the Pentium MMX.
-	// MOVQ 0x8(%ESP), %MM0
-	BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
-	// MOVQ %MM0, (%EAX)
-	BYTE $0x0f; BYTE $0x7f; BYTE $0x00 
-	EMMS
+	// FILDQ 0x8(%ESP)
+	BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
+	// FISTPQ (%EAX)
+	BYTE $0xdf; BYTE $0x38
 	// This is essentially a no-op, but it provides required memory fencing.
 	// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
 	XORL	AX, AX