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https://github.com/balena-os/balena-supervisor.git
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gosuper: support i386 platforms without MMX instructions
The intel quark and the gallileo have an x86 CPU that does not have MMX extensions. Use a patched go that does not require those instructions for atomics, and also enable the GO386=387 flag. Signed-off-by: Petros Angelatos <petrosagg@gmail.com>
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Petros Angelatos
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commit
c7a7ba93fb
@ -1,17 +1,44 @@
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# Build golang supervisor
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FROM golang:1.6
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FROM debian:jessie
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RUN apt-get update \
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&& apt-get install -y \
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build-essential \
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curl \
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rsync \
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upx-ucl \
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&& rm -rf /var/lib/apt/lists/
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ENV GOLANG_VERSION 1.6.3
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ENV GOLANG_DOWNLOAD_URL https://golang.org/dl/go$GOLANG_VERSION.linux-amd64.tar.gz
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ENV GOLANG_DOWNLOAD_SHA256 cdde5e08530c0579255d6153b08fdb3b8e47caabbe717bc7bcd7561275a87aeb
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COPY go-${GOLANG_VERSION}-patches /go-${GOLANG_VERSION}-patches
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RUN mkdir /usr/src/go \
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&& cd /usr/src/go \
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&& curl -L -o go.tar.gz $GOLANG_DOWNLOAD_URL \
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&& echo "${GOLANG_DOWNLOAD_SHA256} go.tar.gz" | sha256sum -c - \
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&& tar xzf go.tar.gz -C /usr/local \
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&& cd /usr/src \
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&& rm -rf go \
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&& export GOROOT_BOOTSTRAP=/usr/local/go-bootstrap \
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&& cp -r /usr/local/go /usr/local/go-bootstrap \
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&& cd /usr/local/go/src \
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&& patch -p2 -i /go-${GOLANG_VERSION}-patches/0001-Revert-runtime-check-and-fail-early-with-a-message-i.patch \
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&& patch -p2 -i /go-${GOLANG_VERSION}-patches/0002-implement-atomic-quadword-ops-with-FILD-FISTP.patch \
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&& ./make.bash \
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&& rm -rf /usr/local/go-bootstrap
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ENV GOPATH /go
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ENV PATH $GOPATH/bin:/usr/local/go/bin:$PATH
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COPY . /go/src/resin-supervisor/gosuper
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WORKDIR /go/src/resin-supervisor/gosuper
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ENV GOOS linux
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ENV GO386=387
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ARG GOARCH=amd64
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ARG GOARM=''
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@ -0,0 +1,81 @@
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From 0ea3a41d2dc8b222093f191e6c2b7c3c89ac4e87 Mon Sep 17 00:00:00 2001
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From: Petros Angelatos <petrosagg@gmail.com>
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Date: Thu, 20 Oct 2016 20:20:56 -0700
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Subject: [PATCH 1/2] Revert "runtime: check and fail early with a message if
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MMX is not available on 386"
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This reverts commit 35e84546d7c3cc599dd5bf31ad86bf8d3d841d04.
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---
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src/runtime/asm_386.s | 42 ------------------------------------------
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1 file changed, 42 deletions(-)
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diff --git a/src/runtime/asm_386.s b/src/runtime/asm_386.s
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index 4181859..942446e 100644
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--- a/src/runtime/asm_386.s
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+++ b/src/runtime/asm_386.s
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@@ -26,32 +26,6 @@ TEXT runtime·rt0_go(SB),NOSPLIT,$0
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MOVL SP, (g_stack+stack_hi)(BP)
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// find out information about the processor we're on
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-#ifdef GOOS_nacl // NaCl doesn't like PUSHFL/POPFL
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- JMP has_cpuid
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-#else
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- // first see if CPUID instruction is supported.
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- PUSHFL
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- PUSHFL
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- XORL $(1<<21), 0(SP) // flip ID bit
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- POPFL
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- PUSHFL
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- POPL AX
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- XORL 0(SP), AX
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- POPFL // restore EFLAGS
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- TESTL $(1<<21), AX
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- JNE has_cpuid
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-#endif
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-
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-bad_proc: // show that the program requires MMX.
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- MOVL $2, 0(SP)
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- MOVL $bad_proc_msg<>(SB), 4(SP)
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- MOVL $0x3d, 8(SP)
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- CALL runtime·write(SB)
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- MOVL $1, 0(SP)
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- CALL runtime·exit(SB)
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- INT $3
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-
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-has_cpuid:
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MOVL $0, AX
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CPUID
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CMPL AX, $0
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@@ -74,11 +48,6 @@ notintel:
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MOVL CX, AX // Move to global variable clobbers CX when generating PIC
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MOVL AX, runtime·cpuid_ecx(SB)
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MOVL DX, runtime·cpuid_edx(SB)
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-
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- // Check for MMX support
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- TESTL $(1<<23), DX // MMX
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- JZ bad_proc
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-
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nocpuinfo:
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// if there is an _cgo_init, call it to let it
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@@ -160,17 +129,6 @@ ok:
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INT $3
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RET
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-DATA bad_proc_msg<>+0x00(SB)/8, $"This pro"
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-DATA bad_proc_msg<>+0x08(SB)/8, $"gram can"
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-DATA bad_proc_msg<>+0x10(SB)/8, $" only be"
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-DATA bad_proc_msg<>+0x18(SB)/8, $" run on "
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-DATA bad_proc_msg<>+0x20(SB)/8, $"processe"
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-DATA bad_proc_msg<>+0x28(SB)/8, $"rs with "
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-DATA bad_proc_msg<>+0x30(SB)/8, $"MMX supp"
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-DATA bad_proc_msg<>+0x38(SB)/4, $"ort."
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-DATA bad_proc_msg<>+0x3c(SB)/1, $0xa
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-GLOBL bad_proc_msg<>(SB), RODATA, $0x3d
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-
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DATA runtime·mainPC+0(SB)/4,$runtime·main(SB)
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GLOBL runtime·mainPC(SB),RODATA,$4
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--
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2.10.0
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@ -0,0 +1,91 @@
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From 973d55e9e319a895e406c89413563a2fc787e98c Mon Sep 17 00:00:00 2001
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From: Petros Angelatos <petrosagg@gmail.com>
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Date: Tue, 18 Oct 2016 08:13:44 -0700
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Subject: [PATCH 2/2] implement atomic quadword ops with FILD/FISTP
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Signed-off-by: Petros Angelatos <petrosagg@gmail.com>
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---
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src/runtime/internal/atomic/asm_386.s | 21 ++++++++-------------
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src/sync/atomic/asm_386.s | 20 ++++++++------------
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2 files changed, 16 insertions(+), 25 deletions(-)
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diff --git a/src/runtime/internal/atomic/asm_386.s b/src/runtime/internal/atomic/asm_386.s
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index ce84fd8..cd91023 100644
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--- a/src/runtime/internal/atomic/asm_386.s
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+++ b/src/runtime/internal/atomic/asm_386.s
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@@ -121,12 +121,10 @@ TEXT runtime∕internal∕atomic·Load64(SB), NOSPLIT, $0-12
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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LEAL ret_lo+4(FP), BX
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0(%EBX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x03
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ (%EBX)
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+ BYTE $0xdf; BYTE $0x3b
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RET
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// void runtime∕internal∕atomic·Store64(uint64 volatile* addr, uint64 v);
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@@ -135,13 +133,10 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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MOVL $0, AX
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diff --git a/src/sync/atomic/asm_386.s b/src/sync/atomic/asm_386.s
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index 383d759..b706047 100644
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--- a/src/sync/atomic/asm_386.s
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+++ b/src/sync/atomic/asm_386.s
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@@ -157,12 +157,10 @@ TEXT ·LoadUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0x8(%ESP)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- EMMS
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x7c; BYTE $0x24; BYTE $0x08
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RET
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TEXT ·LoadUintptr(SB),NOSPLIT,$0-8
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@@ -188,12 +186,10 @@ TEXT ·StoreUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- EMMS
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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XORL AX, AX
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--
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2.10.0
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