mirror of
https://github.com/balena-os/balena-supervisor.git
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92 lines
3.1 KiB
Diff
92 lines
3.1 KiB
Diff
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From 973d55e9e319a895e406c89413563a2fc787e98c Mon Sep 17 00:00:00 2001
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From: Petros Angelatos <petrosagg@gmail.com>
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Date: Tue, 18 Oct 2016 08:13:44 -0700
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Subject: [PATCH 2/2] implement atomic quadword ops with FILD/FISTP
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Signed-off-by: Petros Angelatos <petrosagg@gmail.com>
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---
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src/runtime/internal/atomic/asm_386.s | 21 ++++++++-------------
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src/sync/atomic/asm_386.s | 20 ++++++++------------
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2 files changed, 16 insertions(+), 25 deletions(-)
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diff --git a/src/runtime/internal/atomic/asm_386.s b/src/runtime/internal/atomic/asm_386.s
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index ce84fd8..cd91023 100644
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--- a/src/runtime/internal/atomic/asm_386.s
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+++ b/src/runtime/internal/atomic/asm_386.s
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@@ -121,12 +121,10 @@ TEXT runtime∕internal∕atomic·Load64(SB), NOSPLIT, $0-12
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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LEAL ret_lo+4(FP), BX
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0(%EBX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x03
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ (%EBX)
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+ BYTE $0xdf; BYTE $0x3b
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RET
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// void runtime∕internal∕atomic·Store64(uint64 volatile* addr, uint64 v);
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@@ -135,13 +133,10 @@ TEXT runtime∕internal∕atomic·Store64(SB), NOSPLIT, $0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- // EMMS
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- BYTE $0x0F; BYTE $0x77
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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MOVL $0, AX
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diff --git a/src/sync/atomic/asm_386.s b/src/sync/atomic/asm_386.s
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index 383d759..b706047 100644
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--- a/src/sync/atomic/asm_386.s
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+++ b/src/sync/atomic/asm_386.s
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@@ -157,12 +157,10 @@ TEXT ·LoadUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ (%EAX), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x00
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- // MOVQ %MM0, 0x8(%ESP)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- EMMS
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+ // FILDQ (%EAX)
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+ BYTE $0xdf; BYTE $0x28
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+ // FISTPQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x7c; BYTE $0x24; BYTE $0x08
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RET
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TEXT ·LoadUintptr(SB),NOSPLIT,$0-8
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@@ -188,12 +186,10 @@ TEXT ·StoreUint64(SB),NOSPLIT,$0-12
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TESTL $7, AX
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JZ 2(PC)
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MOVL 0, AX // crash with nil ptr deref
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- // MOVQ and EMMS were introduced on the Pentium MMX.
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- // MOVQ 0x8(%ESP), %MM0
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- BYTE $0x0f; BYTE $0x6f; BYTE $0x44; BYTE $0x24; BYTE $0x08
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- // MOVQ %MM0, (%EAX)
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- BYTE $0x0f; BYTE $0x7f; BYTE $0x00
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- EMMS
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+ // FILDQ 0x8(%ESP)
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+ BYTE $0xdf; BYTE $0x6c; BYTE $0x24; BYTE $0x08
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+ // FISTPQ (%EAX)
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+ BYTE $0xdf; BYTE $0x38
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// This is essentially a no-op, but it provides required memory fencing.
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// It can be replaced with MFENCE, but MFENCE was introduced only on the Pentium4 (SSE2).
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XORL AX, AX
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--
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2.10.0
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