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https://github.com/szehl/ath9k-hmac.git
synced 2024-12-22 06:58:01 +00:00
466 lines
9.9 KiB
C
Executable File
466 lines
9.9 KiB
C
Executable File
/*
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* Elonics E4000 silicon tuner driver
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*
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* Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#include "e4000_priv.h"
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#include <linux/math64.h>
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/* Max transfer size done by I2C transfer functions */
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#define MAX_XFER_SIZE 64
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/* write multiple registers */
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static int e4000_wr_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
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{
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int ret;
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u8 buf[MAX_XFER_SIZE];
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struct i2c_msg msg[1] = {
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{
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.addr = priv->cfg->i2c_addr,
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.flags = 0,
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.len = 1 + len,
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.buf = buf,
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}
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};
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if (1 + len > sizeof(buf)) {
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dev_warn(&priv->i2c->dev,
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"%s: i2c wr reg=%04x: len=%d is too big!\n",
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KBUILD_MODNAME, reg, len);
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return -EINVAL;
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}
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buf[0] = reg;
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memcpy(&buf[1], val, len);
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ret = i2c_transfer(priv->i2c, msg, 1);
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if (ret == 1) {
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ret = 0;
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} else {
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dev_warn(&priv->i2c->dev,
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"%s: i2c wr failed=%d reg=%02x len=%d\n",
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KBUILD_MODNAME, ret, reg, len);
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ret = -EREMOTEIO;
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}
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return ret;
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}
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/* read multiple registers */
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static int e4000_rd_regs(struct e4000_priv *priv, u8 reg, u8 *val, int len)
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{
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int ret;
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u8 buf[MAX_XFER_SIZE];
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struct i2c_msg msg[2] = {
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{
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.addr = priv->cfg->i2c_addr,
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.flags = 0,
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.len = 1,
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.buf = ®,
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}, {
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.addr = priv->cfg->i2c_addr,
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.flags = I2C_M_RD,
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.len = len,
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.buf = buf,
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}
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};
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if (len > sizeof(buf)) {
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dev_warn(&priv->i2c->dev,
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"%s: i2c rd reg=%04x: len=%d is too big!\n",
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KBUILD_MODNAME, reg, len);
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return -EINVAL;
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}
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ret = i2c_transfer(priv->i2c, msg, 2);
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if (ret == 2) {
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memcpy(val, buf, len);
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ret = 0;
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} else {
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dev_warn(&priv->i2c->dev,
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"%s: i2c rd failed=%d reg=%02x len=%d\n",
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KBUILD_MODNAME, ret, reg, len);
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ret = -EREMOTEIO;
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}
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return ret;
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}
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/* write single register */
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static int e4000_wr_reg(struct e4000_priv *priv, u8 reg, u8 val)
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{
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return e4000_wr_regs(priv, reg, &val, 1);
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}
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/* read single register */
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static int e4000_rd_reg(struct e4000_priv *priv, u8 reg, u8 *val)
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{
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return e4000_rd_regs(priv, reg, val, 1);
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}
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static int e4000_init(struct dvb_frontend *fe)
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{
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struct e4000_priv *priv = fe->tuner_priv;
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int ret;
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dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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/* dummy I2C to ensure I2C wakes up */
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ret = e4000_wr_reg(priv, 0x02, 0x40);
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/* reset */
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ret = e4000_wr_reg(priv, 0x00, 0x01);
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if (ret < 0)
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goto err;
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/* disable output clock */
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ret = e4000_wr_reg(priv, 0x06, 0x00);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x7a, 0x96);
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if (ret < 0)
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goto err;
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/* configure gains */
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ret = e4000_wr_regs(priv, 0x7e, "\x01\xfe", 2);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x82, 0x00);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x24, 0x05);
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if (ret < 0)
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goto err;
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ret = e4000_wr_regs(priv, 0x87, "\x20\x01", 2);
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if (ret < 0)
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goto err;
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ret = e4000_wr_regs(priv, 0x9f, "\x7f\x07", 2);
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if (ret < 0)
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goto err;
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/* DC offset control */
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ret = e4000_wr_reg(priv, 0x2d, 0x1f);
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if (ret < 0)
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goto err;
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ret = e4000_wr_regs(priv, 0x70, "\x01\x01", 2);
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if (ret < 0)
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goto err;
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/* gain control */
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ret = e4000_wr_reg(priv, 0x1a, 0x17);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x1f, 0x1a);
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if (ret < 0)
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goto err;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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return 0;
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err:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int e4000_sleep(struct dvb_frontend *fe)
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{
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struct e4000_priv *priv = fe->tuner_priv;
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int ret;
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dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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ret = e4000_wr_reg(priv, 0x00, 0x00);
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if (ret < 0)
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goto err;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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return 0;
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err:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int e4000_set_params(struct dvb_frontend *fe)
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{
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struct e4000_priv *priv = fe->tuner_priv;
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struct dtv_frontend_properties *c = &fe->dtv_property_cache;
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int ret, i, sigma_delta;
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unsigned int f_vco;
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u8 buf[5], i_data[4], q_data[4];
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dev_dbg(&priv->i2c->dev,
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"%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
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__func__, c->delivery_system, c->frequency,
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c->bandwidth_hz);
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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/* gain control manual */
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ret = e4000_wr_reg(priv, 0x1a, 0x00);
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if (ret < 0)
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goto err;
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/* PLL */
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for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
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if (c->frequency <= e4000_pll_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(e4000_pll_lut))
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goto err;
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/*
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* Note: Currently f_vco overflows when c->frequency is 1 073 741 824 Hz
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* or more.
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*/
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f_vco = c->frequency * e4000_pll_lut[i].mul;
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sigma_delta = div_u64(0x10000ULL * (f_vco % priv->cfg->clock), priv->cfg->clock);
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buf[0] = f_vco / priv->cfg->clock;
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buf[1] = (sigma_delta >> 0) & 0xff;
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buf[2] = (sigma_delta >> 8) & 0xff;
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buf[3] = 0x00;
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buf[4] = e4000_pll_lut[i].div;
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dev_dbg(&priv->i2c->dev, "%s: f_vco=%u pll div=%d sigma_delta=%04x\n",
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__func__, f_vco, buf[0], sigma_delta);
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ret = e4000_wr_regs(priv, 0x09, buf, 5);
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if (ret < 0)
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goto err;
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/* LNA filter (RF filter) */
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for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
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if (c->frequency <= e400_lna_filter_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(e400_lna_filter_lut))
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goto err;
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ret = e4000_wr_reg(priv, 0x10, e400_lna_filter_lut[i].val);
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if (ret < 0)
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goto err;
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/* IF filters */
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for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
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if (c->bandwidth_hz <= e4000_if_filter_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(e4000_if_filter_lut))
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goto err;
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buf[0] = e4000_if_filter_lut[i].reg11_val;
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buf[1] = e4000_if_filter_lut[i].reg12_val;
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ret = e4000_wr_regs(priv, 0x11, buf, 2);
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if (ret < 0)
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goto err;
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/* frequency band */
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for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
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if (c->frequency <= e4000_band_lut[i].freq)
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break;
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}
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if (i == ARRAY_SIZE(e4000_band_lut))
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goto err;
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ret = e4000_wr_reg(priv, 0x07, e4000_band_lut[i].reg07_val);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x78, e4000_band_lut[i].reg78_val);
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if (ret < 0)
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goto err;
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/* DC offset */
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for (i = 0; i < 4; i++) {
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if (i == 0)
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ret = e4000_wr_regs(priv, 0x15, "\x00\x7e\x24", 3);
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else if (i == 1)
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ret = e4000_wr_regs(priv, 0x15, "\x00\x7f", 2);
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else if (i == 2)
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ret = e4000_wr_regs(priv, 0x15, "\x01", 1);
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else
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ret = e4000_wr_regs(priv, 0x16, "\x7e", 1);
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if (ret < 0)
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goto err;
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ret = e4000_wr_reg(priv, 0x29, 0x01);
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if (ret < 0)
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goto err;
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ret = e4000_rd_regs(priv, 0x2a, buf, 3);
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if (ret < 0)
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goto err;
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i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
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q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
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}
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swap(q_data[2], q_data[3]);
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swap(i_data[2], i_data[3]);
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ret = e4000_wr_regs(priv, 0x50, q_data, 4);
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if (ret < 0)
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goto err;
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ret = e4000_wr_regs(priv, 0x60, i_data, 4);
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if (ret < 0)
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goto err;
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/* gain control auto */
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ret = e4000_wr_reg(priv, 0x1a, 0x17);
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if (ret < 0)
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goto err;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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return 0;
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err:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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dev_dbg(&priv->i2c->dev, "%s: failed=%d\n", __func__, ret);
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return ret;
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}
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static int e4000_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
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{
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struct e4000_priv *priv = fe->tuner_priv;
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dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
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*frequency = 0; /* Zero-IF */
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return 0;
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}
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static int e4000_release(struct dvb_frontend *fe)
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{
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struct e4000_priv *priv = fe->tuner_priv;
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dev_dbg(&priv->i2c->dev, "%s:\n", __func__);
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kfree(fe->tuner_priv);
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return 0;
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}
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static const struct dvb_tuner_ops e4000_tuner_ops = {
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.info = {
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.name = "Elonics E4000",
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.frequency_min = 174000000,
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.frequency_max = 862000000,
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},
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.release = e4000_release,
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.init = e4000_init,
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.sleep = e4000_sleep,
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.set_params = e4000_set_params,
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.get_if_frequency = e4000_get_if_frequency,
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};
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struct dvb_frontend *e4000_attach(struct dvb_frontend *fe,
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struct i2c_adapter *i2c, const struct e4000_config *cfg)
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{
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struct e4000_priv *priv;
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int ret;
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u8 chip_id;
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 1);
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priv = kzalloc(sizeof(struct e4000_priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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dev_err(&i2c->dev, "%s: kzalloc() failed\n", KBUILD_MODNAME);
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goto err;
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}
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priv->cfg = cfg;
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priv->i2c = i2c;
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/* check if the tuner is there */
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ret = e4000_rd_reg(priv, 0x02, &chip_id);
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if (ret < 0)
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goto err;
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dev_dbg(&priv->i2c->dev, "%s: chip_id=%02x\n", __func__, chip_id);
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if (chip_id != 0x40)
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goto err;
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/* put sleep as chip seems to be in normal mode by default */
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ret = e4000_wr_reg(priv, 0x00, 0x00);
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if (ret < 0)
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goto err;
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dev_info(&priv->i2c->dev,
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"%s: Elonics E4000 successfully identified\n",
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KBUILD_MODNAME);
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fe->tuner_priv = priv;
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memcpy(&fe->ops.tuner_ops, &e4000_tuner_ops,
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sizeof(struct dvb_tuner_ops));
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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return fe;
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err:
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if (fe->ops.i2c_gate_ctrl)
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fe->ops.i2c_gate_ctrl(fe, 0);
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dev_dbg(&i2c->dev, "%s: failed=%d\n", __func__, ret);
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kfree(priv);
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return NULL;
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}
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EXPORT_SYMBOL(e4000_attach);
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MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
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MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
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MODULE_LICENSE("GPL");
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