mirror of
https://github.com/szehl/ath9k-hmac.git
synced 2024-12-23 15:32:43 +00:00
340 lines
7.4 KiB
C
340 lines
7.4 KiB
C
/*
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* Copyright (C) ST-Ericsson SA 2010
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*
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* License Terms: GNU General Public License v2
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*
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* Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
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* Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
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* Daniel Willerud <daniel.willerud@stericsson.com> for ST-Ericsson
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*/
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#ifndef __LINUX_MFD_AB8500_REGULATOR_H
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#define __LINUX_MFD_AB8500_REGULATOR_H
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#include <linux/platform_device.h>
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/* AB8500 regulators */
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enum ab8500_regulator_id {
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AB8500_LDO_AUX1,
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AB8500_LDO_AUX2,
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AB8500_LDO_AUX3,
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AB8500_LDO_INTCORE,
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AB8500_LDO_TVOUT,
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AB8500_LDO_AUDIO,
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AB8500_LDO_ANAMIC1,
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AB8500_LDO_ANAMIC2,
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AB8500_LDO_DMIC,
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AB8500_LDO_ANA,
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AB8500_NUM_REGULATORS,
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};
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/* AB8505 regulators */
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enum ab8505_regulator_id {
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AB8505_LDO_AUX1,
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AB8505_LDO_AUX2,
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AB8505_LDO_AUX3,
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AB8505_LDO_AUX4,
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AB8505_LDO_AUX5,
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AB8505_LDO_AUX6,
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AB8505_LDO_INTCORE,
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AB8505_LDO_ADC,
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AB8505_LDO_USB,
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AB8505_LDO_AUDIO,
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AB8505_LDO_ANAMIC1,
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AB8505_LDO_ANAMIC2,
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AB8505_LDO_AUX8,
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AB8505_LDO_ANA,
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AB8505_SYSCLKREQ_2,
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AB8505_SYSCLKREQ_4,
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AB8505_NUM_REGULATORS,
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};
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/* AB9540 regulators */
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enum ab9540_regulator_id {
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AB9540_LDO_AUX1,
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AB9540_LDO_AUX2,
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AB9540_LDO_AUX3,
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AB9540_LDO_AUX4,
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AB9540_LDO_INTCORE,
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AB9540_LDO_TVOUT,
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AB9540_LDO_USB,
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AB9540_LDO_AUDIO,
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AB9540_LDO_ANAMIC1,
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AB9540_LDO_ANAMIC2,
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AB9540_LDO_DMIC,
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AB9540_LDO_ANA,
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AB9540_SYSCLKREQ_2,
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AB9540_SYSCLKREQ_4,
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AB9540_NUM_REGULATORS,
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};
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/* AB8540 regulators */
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enum ab8540_regulator_id {
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AB8540_LDO_AUX1,
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AB8540_LDO_AUX2,
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AB8540_LDO_AUX3,
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AB8540_LDO_AUX4,
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AB8540_LDO_AUX5,
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AB8540_LDO_AUX6,
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AB8540_LDO_INTCORE,
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AB8540_LDO_TVOUT,
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AB8540_LDO_AUDIO,
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AB8540_LDO_ANAMIC1,
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AB8540_LDO_ANAMIC2,
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AB8540_LDO_DMIC,
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AB8540_LDO_ANA,
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AB8540_LDO_SDIO,
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AB8540_SYSCLKREQ_2,
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AB8540_SYSCLKREQ_4,
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AB8540_NUM_REGULATORS,
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};
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/* AB8500, AB8505, and AB9540 register initialization */
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struct ab8500_regulator_reg_init {
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int id;
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u8 mask;
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u8 value;
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};
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#define INIT_REGULATOR_REGISTER(_id, _mask, _value) \
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{ \
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.id = _id, \
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.mask = _mask, \
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.value = _value, \
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}
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/* AB8500 registers */
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enum ab8500_regulator_reg {
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AB8500_REGUREQUESTCTRL2,
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AB8500_REGUREQUESTCTRL3,
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AB8500_REGUREQUESTCTRL4,
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AB8500_REGUSYSCLKREQ1HPVALID1,
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AB8500_REGUSYSCLKREQ1HPVALID2,
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AB8500_REGUHWHPREQ1VALID1,
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AB8500_REGUHWHPREQ1VALID2,
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AB8500_REGUHWHPREQ2VALID1,
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AB8500_REGUHWHPREQ2VALID2,
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AB8500_REGUSWHPREQVALID1,
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AB8500_REGUSWHPREQVALID2,
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AB8500_REGUSYSCLKREQVALID1,
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AB8500_REGUSYSCLKREQVALID2,
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AB8500_REGUMISC1,
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AB8500_VAUDIOSUPPLY,
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AB8500_REGUCTRL1VAMIC,
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AB8500_VPLLVANAREGU,
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AB8500_VREFDDR,
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AB8500_EXTSUPPLYREGU,
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AB8500_VAUX12REGU,
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AB8500_VRF1VAUX3REGU,
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AB8500_VAUX1SEL,
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AB8500_VAUX2SEL,
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AB8500_VRF1VAUX3SEL,
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AB8500_REGUCTRL2SPARE,
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AB8500_REGUCTRLDISCH,
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AB8500_REGUCTRLDISCH2,
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AB8500_NUM_REGULATOR_REGISTERS,
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};
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/* AB8505 registers */
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enum ab8505_regulator_reg {
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AB8505_REGUREQUESTCTRL1,
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AB8505_REGUREQUESTCTRL2,
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AB8505_REGUREQUESTCTRL3,
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AB8505_REGUREQUESTCTRL4,
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AB8505_REGUSYSCLKREQ1HPVALID1,
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AB8505_REGUSYSCLKREQ1HPVALID2,
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AB8505_REGUHWHPREQ1VALID1,
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AB8505_REGUHWHPREQ1VALID2,
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AB8505_REGUHWHPREQ2VALID1,
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AB8505_REGUHWHPREQ2VALID2,
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AB8505_REGUSWHPREQVALID1,
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AB8505_REGUSWHPREQVALID2,
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AB8505_REGUSYSCLKREQVALID1,
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AB8505_REGUSYSCLKREQVALID2,
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AB8505_REGUVAUX4REQVALID,
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AB8505_REGUMISC1,
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AB8505_VAUDIOSUPPLY,
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AB8505_REGUCTRL1VAMIC,
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AB8505_VSMPSAREGU,
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AB8505_VSMPSBREGU,
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AB8505_VSAFEREGU, /* NOTE! PRCMU register */
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AB8505_VPLLVANAREGU,
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AB8505_EXTSUPPLYREGU,
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AB8505_VAUX12REGU,
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AB8505_VRF1VAUX3REGU,
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AB8505_VSMPSASEL1,
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AB8505_VSMPSASEL2,
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AB8505_VSMPSASEL3,
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AB8505_VSMPSBSEL1,
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AB8505_VSMPSBSEL2,
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AB8505_VSMPSBSEL3,
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AB8505_VSAFESEL1, /* NOTE! PRCMU register */
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AB8505_VSAFESEL2, /* NOTE! PRCMU register */
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AB8505_VSAFESEL3, /* NOTE! PRCMU register */
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AB8505_VAUX1SEL,
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AB8505_VAUX2SEL,
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AB8505_VRF1VAUX3SEL,
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AB8505_VAUX4REQCTRL,
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AB8505_VAUX4REGU,
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AB8505_VAUX4SEL,
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AB8505_REGUCTRLDISCH,
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AB8505_REGUCTRLDISCH2,
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AB8505_REGUCTRLDISCH3,
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AB8505_CTRLVAUX5,
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AB8505_CTRLVAUX6,
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AB8505_NUM_REGULATOR_REGISTERS,
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};
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/* AB9540 registers */
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enum ab9540_regulator_reg {
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AB9540_REGUREQUESTCTRL1,
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AB9540_REGUREQUESTCTRL2,
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AB9540_REGUREQUESTCTRL3,
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AB9540_REGUREQUESTCTRL4,
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AB9540_REGUSYSCLKREQ1HPVALID1,
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AB9540_REGUSYSCLKREQ1HPVALID2,
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AB9540_REGUHWHPREQ1VALID1,
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AB9540_REGUHWHPREQ1VALID2,
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AB9540_REGUHWHPREQ2VALID1,
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AB9540_REGUHWHPREQ2VALID2,
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AB9540_REGUSWHPREQVALID1,
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AB9540_REGUSWHPREQVALID2,
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AB9540_REGUSYSCLKREQVALID1,
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AB9540_REGUSYSCLKREQVALID2,
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AB9540_REGUVAUX4REQVALID,
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AB9540_REGUMISC1,
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AB9540_VAUDIOSUPPLY,
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AB9540_REGUCTRL1VAMIC,
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AB9540_VSMPS1REGU,
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AB9540_VSMPS2REGU,
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AB9540_VSMPS3REGU, /* NOTE! PRCMU register */
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AB9540_VPLLVANAREGU,
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AB9540_EXTSUPPLYREGU,
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AB9540_VAUX12REGU,
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AB9540_VRF1VAUX3REGU,
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AB9540_VSMPS1SEL1,
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AB9540_VSMPS1SEL2,
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AB9540_VSMPS1SEL3,
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AB9540_VSMPS2SEL1,
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AB9540_VSMPS2SEL2,
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AB9540_VSMPS2SEL3,
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AB9540_VSMPS3SEL1, /* NOTE! PRCMU register */
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AB9540_VSMPS3SEL2, /* NOTE! PRCMU register */
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AB9540_VAUX1SEL,
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AB9540_VAUX2SEL,
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AB9540_VRF1VAUX3SEL,
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AB9540_REGUCTRL2SPARE,
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AB9540_VAUX4REQCTRL,
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AB9540_VAUX4REGU,
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AB9540_VAUX4SEL,
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AB9540_REGUCTRLDISCH,
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AB9540_REGUCTRLDISCH2,
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AB9540_REGUCTRLDISCH3,
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AB9540_NUM_REGULATOR_REGISTERS,
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};
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/* AB8540 registers */
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enum ab8540_regulator_reg {
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AB8540_REGUREQUESTCTRL1,
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AB8540_REGUREQUESTCTRL2,
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AB8540_REGUREQUESTCTRL3,
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AB8540_REGUREQUESTCTRL4,
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AB8540_REGUSYSCLKREQ1HPVALID1,
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AB8540_REGUSYSCLKREQ1HPVALID2,
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AB8540_REGUHWHPREQ1VALID1,
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AB8540_REGUHWHPREQ1VALID2,
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AB8540_REGUHWHPREQ2VALID1,
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AB8540_REGUHWHPREQ2VALID2,
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AB8540_REGUSWHPREQVALID1,
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AB8540_REGUSWHPREQVALID2,
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AB8540_REGUSYSCLKREQVALID1,
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AB8540_REGUSYSCLKREQVALID2,
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AB8540_REGUVAUX4REQVALID,
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AB8540_REGUVAUX5REQVALID,
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AB8540_REGUVAUX6REQVALID,
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AB8540_REGUVCLKBREQVALID,
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AB8540_REGUVRF1REQVALID,
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AB8540_REGUMISC1,
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AB8540_VAUDIOSUPPLY,
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AB8540_REGUCTRL1VAMIC,
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AB8540_VHSIC,
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AB8540_VSDIO,
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AB8540_VSMPS1REGU,
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AB8540_VSMPS2REGU,
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AB8540_VSMPS3REGU,
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AB8540_VPLLVANAREGU,
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AB8540_EXTSUPPLYREGU,
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AB8540_VAUX12REGU,
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AB8540_VRF1VAUX3REGU,
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AB8540_VSMPS1SEL1,
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AB8540_VSMPS1SEL2,
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AB8540_VSMPS1SEL3,
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AB8540_VSMPS2SEL1,
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AB8540_VSMPS2SEL2,
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AB8540_VSMPS2SEL3,
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AB8540_VSMPS3SEL1,
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AB8540_VSMPS3SEL2,
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AB8540_VAUX1SEL,
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AB8540_VAUX2SEL,
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AB8540_VRF1VAUX3SEL,
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AB8540_REGUCTRL2SPARE,
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AB8540_VAUX4REQCTRL,
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AB8540_VAUX4REGU,
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AB8540_VAUX4SEL,
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AB8540_VAUX5REQCTRL,
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AB8540_VAUX5REGU,
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AB8540_VAUX5SEL,
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AB8540_VAUX6REQCTRL,
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AB8540_VAUX6REGU,
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AB8540_VAUX6SEL,
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AB8540_VCLKBREQCTRL,
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AB8540_VCLKBREGU,
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AB8540_VCLKBSEL,
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AB8540_VRF1REQCTRL,
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AB8540_REGUCTRLDISCH,
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AB8540_REGUCTRLDISCH2,
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AB8540_REGUCTRLDISCH3,
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AB8540_REGUCTRLDISCH4,
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AB8540_VSIMSYSCLKCTRL,
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AB8540_VANAVPLLSEL,
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AB8540_NUM_REGULATOR_REGISTERS,
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};
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/* AB8500 external regulators */
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struct ab8500_ext_regulator_cfg {
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bool hwreq; /* requires hw mode or high power mode */
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};
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enum ab8500_ext_regulator_id {
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AB8500_EXT_SUPPLY1,
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AB8500_EXT_SUPPLY2,
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AB8500_EXT_SUPPLY3,
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AB8500_NUM_EXT_REGULATORS,
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};
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/* AB8500 regulator platform data */
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struct ab8500_regulator_platform_data {
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int num_reg_init;
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struct ab8500_regulator_reg_init *reg_init;
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int num_regulator;
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struct regulator_init_data *regulator;
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int num_ext_regulator;
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struct regulator_init_data *ext_regulator;
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};
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#ifdef CONFIG_REGULATOR_AB8500_DEBUG
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int ab8500_regulator_debug_init(struct platform_device *pdev);
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int ab8500_regulator_debug_exit(struct platform_device *pdev);
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#else
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static inline int ab8500_regulator_debug_init(struct platform_device *pdev)
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{
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return 0;
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}
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static inline int ab8500_regulator_debug_exit(struct platform_device *pdev)
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{
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return 0;
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}
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#endif
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#endif
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