mirror of
https://github.com/zerotier/ZeroTierOne.git
synced 2024-12-24 15:16:40 +00:00
190 lines
3.9 KiB
ArmAsm
190 lines
3.9 KiB
ArmAsm
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# qhasm: int64 rp
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# qhasm: int64 xp
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# qhasm: int64 yp
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# qhasm: input rp
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# qhasm: input xp
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# qhasm: input yp
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# qhasm: int64 r0
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# qhasm: int64 r1
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# qhasm: int64 r2
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# qhasm: int64 r3
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# qhasm: int64 addt0
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# qhasm: int64 addt1
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# qhasm: int64 caller1
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# qhasm: int64 caller2
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# qhasm: int64 caller3
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# qhasm: int64 caller4
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# qhasm: int64 caller5
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# qhasm: int64 caller6
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# qhasm: int64 caller7
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# qhasm: caller caller1
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# qhasm: caller caller2
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# qhasm: caller caller3
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# qhasm: caller caller4
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# qhasm: caller caller5
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# qhasm: caller caller6
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# qhasm: caller caller7
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# qhasm: stack64 caller1_stack
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# qhasm: stack64 caller2_stack
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# qhasm: stack64 caller3_stack
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# qhasm: stack64 caller4_stack
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# qhasm: stack64 caller5_stack
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# qhasm: stack64 caller6_stack
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# qhasm: stack64 caller7_stack
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# qhasm: enter crypto_sign_ed25519_amd64_64_fe25519_add
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.text
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.p2align 5
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.globl _crypto_sign_ed25519_amd64_64_fe25519_add
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.globl crypto_sign_ed25519_amd64_64_fe25519_add
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_crypto_sign_ed25519_amd64_64_fe25519_add:
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crypto_sign_ed25519_amd64_64_fe25519_add:
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mov %rsp,%r11
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and $31,%r11
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add $0,%r11
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sub %r11,%rsp
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# qhasm: r0 = *(uint64 *)(xp + 0)
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# asm 1: movq 0(<xp=int64#2),>r0=int64#4
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# asm 2: movq 0(<xp=%rsi),>r0=%rcx
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movq 0(%rsi),%rcx
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# qhasm: r1 = *(uint64 *)(xp + 8)
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# asm 1: movq 8(<xp=int64#2),>r1=int64#5
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# asm 2: movq 8(<xp=%rsi),>r1=%r8
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movq 8(%rsi),%r8
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# qhasm: r2 = *(uint64 *)(xp + 16)
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# asm 1: movq 16(<xp=int64#2),>r2=int64#6
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# asm 2: movq 16(<xp=%rsi),>r2=%r9
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movq 16(%rsi),%r9
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# qhasm: r3 = *(uint64 *)(xp + 24)
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# asm 1: movq 24(<xp=int64#2),>r3=int64#2
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# asm 2: movq 24(<xp=%rsi),>r3=%rsi
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movq 24(%rsi),%rsi
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# qhasm: carry? r0 += *(uint64 *)(yp + 0)
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# asm 1: addq 0(<yp=int64#3),<r0=int64#4
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# asm 2: addq 0(<yp=%rdx),<r0=%rcx
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addq 0(%rdx),%rcx
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# qhasm: carry? r1 += *(uint64 *)(yp + 8) + carry
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# asm 1: adcq 8(<yp=int64#3),<r1=int64#5
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# asm 2: adcq 8(<yp=%rdx),<r1=%r8
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adcq 8(%rdx),%r8
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# qhasm: carry? r2 += *(uint64 *)(yp + 16) + carry
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# asm 1: adcq 16(<yp=int64#3),<r2=int64#6
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# asm 2: adcq 16(<yp=%rdx),<r2=%r9
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adcq 16(%rdx),%r9
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# qhasm: carry? r3 += *(uint64 *)(yp + 24) + carry
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# asm 1: adcq 24(<yp=int64#3),<r3=int64#2
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# asm 2: adcq 24(<yp=%rdx),<r3=%rsi
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adcq 24(%rdx),%rsi
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# qhasm: addt0 = 0
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# asm 1: mov $0,>addt0=int64#3
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# asm 2: mov $0,>addt0=%rdx
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mov $0,%rdx
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# qhasm: addt1 = 38
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# asm 1: mov $38,>addt1=int64#7
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# asm 2: mov $38,>addt1=%rax
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mov $38,%rax
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# qhasm: addt1 = addt0 if !carry
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# asm 1: cmovae <addt0=int64#3,<addt1=int64#7
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# asm 2: cmovae <addt0=%rdx,<addt1=%rax
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cmovae %rdx,%rax
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# qhasm: carry? r0 += addt1
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# asm 1: add <addt1=int64#7,<r0=int64#4
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# asm 2: add <addt1=%rax,<r0=%rcx
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add %rax,%rcx
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# qhasm: carry? r1 += addt0 + carry
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# asm 1: adc <addt0=int64#3,<r1=int64#5
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# asm 2: adc <addt0=%rdx,<r1=%r8
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adc %rdx,%r8
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# qhasm: carry? r2 += addt0 + carry
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# asm 1: adc <addt0=int64#3,<r2=int64#6
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# asm 2: adc <addt0=%rdx,<r2=%r9
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adc %rdx,%r9
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# qhasm: carry? r3 += addt0 + carry
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# asm 1: adc <addt0=int64#3,<r3=int64#2
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# asm 2: adc <addt0=%rdx,<r3=%rsi
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adc %rdx,%rsi
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# qhasm: addt0 = addt1 if carry
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# asm 1: cmovc <addt1=int64#7,<addt0=int64#3
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# asm 2: cmovc <addt1=%rax,<addt0=%rdx
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cmovc %rax,%rdx
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# qhasm: r0 += addt0
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# asm 1: add <addt0=int64#3,<r0=int64#4
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# asm 2: add <addt0=%rdx,<r0=%rcx
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add %rdx,%rcx
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# qhasm: *(uint64 *)(rp + 0) = r0
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# asm 1: movq <r0=int64#4,0(<rp=int64#1)
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# asm 2: movq <r0=%rcx,0(<rp=%rdi)
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movq %rcx,0(%rdi)
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# qhasm: *(uint64 *)(rp + 8) = r1
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# asm 1: movq <r1=int64#5,8(<rp=int64#1)
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# asm 2: movq <r1=%r8,8(<rp=%rdi)
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movq %r8,8(%rdi)
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# qhasm: *(uint64 *)(rp + 16) = r2
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# asm 1: movq <r2=int64#6,16(<rp=int64#1)
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# asm 2: movq <r2=%r9,16(<rp=%rdi)
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movq %r9,16(%rdi)
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# qhasm: *(uint64 *)(rp + 24) = r3
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# asm 1: movq <r3=int64#2,24(<rp=int64#1)
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# asm 2: movq <r3=%rsi,24(<rp=%rdi)
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movq %rsi,24(%rdi)
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# qhasm: leave
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add %r11,%rsp
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mov %rdi,%rax
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mov %rsi,%rdx
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ret
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