mirror of
https://github.com/zerotier/ZeroTierOne.git
synced 2024-12-27 08:22:31 +00:00
431 lines
9.1 KiB
ArmAsm
431 lines
9.1 KiB
ArmAsm
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// This file is generated from a similarly-named Perl script in the BoringSSL
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// source tree. Do not edit by hand.
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#if !defined(__has_feature)
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#define __has_feature(x) 0
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#endif
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#if __has_feature(memory_sanitizer) && !defined(OPENSSL_NO_ASM)
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#define OPENSSL_NO_ASM
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#endif
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#if !defined(OPENSSL_NO_ASM)
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#if defined(__aarch64__)
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#include <GFp/arm_arch.h>
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#if __ARM_MAX_ARCH__>=7
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.text
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.arch armv8-a+crypto
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.section .rodata
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.align 5
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.Lrcon:
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.long 0x01,0x01,0x01,0x01
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.long 0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d,0x0c0f0e0d // rotate-n-splat
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.long 0x1b,0x1b,0x1b,0x1b
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.text
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.globl GFp_aes_hw_set_encrypt_key
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.hidden GFp_aes_hw_set_encrypt_key
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.type GFp_aes_hw_set_encrypt_key,%function
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.align 5
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GFp_aes_hw_set_encrypt_key:
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.Lenc_key:
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// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
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AARCH64_VALID_CALL_TARGET
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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mov x3,#-1
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cmp x0,#0
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b.eq .Lenc_key_abort
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cmp x2,#0
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b.eq .Lenc_key_abort
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mov x3,#-2
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cmp w1,#128
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b.lt .Lenc_key_abort
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cmp w1,#256
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b.gt .Lenc_key_abort
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tst w1,#0x3f
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b.ne .Lenc_key_abort
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adrp x3,.Lrcon
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add x3,x3,:lo12:.Lrcon
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cmp w1,#192
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eor v0.16b,v0.16b,v0.16b
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ld1 {v3.16b},[x0],#16
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mov w1,#8 // reuse w1
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ld1 {v1.4s,v2.4s},[x3],#32
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b.lt .Loop128
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// 192-bit key support was removed.
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b .L256
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.align 4
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.Loop128:
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tbl v6.16b,{v3.16b},v2.16b
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ext v5.16b,v0.16b,v3.16b,#12
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st1 {v3.4s},[x2],#16
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aese v6.16b,v0.16b
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subs w1,w1,#1
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v6.16b,v6.16b,v1.16b
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eor v3.16b,v3.16b,v5.16b
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shl v1.16b,v1.16b,#1
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eor v3.16b,v3.16b,v6.16b
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b.ne .Loop128
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ld1 {v1.4s},[x3]
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tbl v6.16b,{v3.16b},v2.16b
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ext v5.16b,v0.16b,v3.16b,#12
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st1 {v3.4s},[x2],#16
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aese v6.16b,v0.16b
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v6.16b,v6.16b,v1.16b
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eor v3.16b,v3.16b,v5.16b
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shl v1.16b,v1.16b,#1
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eor v3.16b,v3.16b,v6.16b
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tbl v6.16b,{v3.16b},v2.16b
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ext v5.16b,v0.16b,v3.16b,#12
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st1 {v3.4s},[x2],#16
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aese v6.16b,v0.16b
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v6.16b,v6.16b,v1.16b
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eor v3.16b,v3.16b,v5.16b
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eor v3.16b,v3.16b,v6.16b
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st1 {v3.4s},[x2]
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add x2,x2,#0x50
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mov w12,#10
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b .Ldone
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// 192-bit key support was removed.
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.align 4
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.L256:
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ld1 {v4.16b},[x0]
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mov w1,#7
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mov w12,#14
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st1 {v3.4s},[x2],#16
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.Loop256:
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tbl v6.16b,{v4.16b},v2.16b
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ext v5.16b,v0.16b,v3.16b,#12
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st1 {v4.4s},[x2],#16
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aese v6.16b,v0.16b
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subs w1,w1,#1
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v3.16b,v3.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v6.16b,v6.16b,v1.16b
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eor v3.16b,v3.16b,v5.16b
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shl v1.16b,v1.16b,#1
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eor v3.16b,v3.16b,v6.16b
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st1 {v3.4s},[x2],#16
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b.eq .Ldone
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dup v6.4s,v3.s[3] // just splat
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ext v5.16b,v0.16b,v4.16b,#12
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aese v6.16b,v0.16b
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eor v4.16b,v4.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v4.16b,v4.16b,v5.16b
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ext v5.16b,v0.16b,v5.16b,#12
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eor v4.16b,v4.16b,v5.16b
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eor v4.16b,v4.16b,v6.16b
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b .Loop256
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.Ldone:
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str w12,[x2]
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mov x3,#0
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.Lenc_key_abort:
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mov x0,x3 // return value
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ldr x29,[sp],#16
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ret
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.size GFp_aes_hw_set_encrypt_key,.-GFp_aes_hw_set_encrypt_key
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.globl GFp_aes_hw_encrypt
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.hidden GFp_aes_hw_encrypt
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.type GFp_aes_hw_encrypt,%function
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.align 5
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GFp_aes_hw_encrypt:
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AARCH64_VALID_CALL_TARGET
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ldr w3,[x2,#240]
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ld1 {v0.4s},[x2],#16
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ld1 {v2.16b},[x0]
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sub w3,w3,#2
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ld1 {v1.4s},[x2],#16
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.Loop_enc:
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aese v2.16b,v0.16b
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aesmc v2.16b,v2.16b
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ld1 {v0.4s},[x2],#16
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subs w3,w3,#2
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aese v2.16b,v1.16b
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aesmc v2.16b,v2.16b
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ld1 {v1.4s},[x2],#16
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b.gt .Loop_enc
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aese v2.16b,v0.16b
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aesmc v2.16b,v2.16b
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ld1 {v0.4s},[x2]
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aese v2.16b,v1.16b
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eor v2.16b,v2.16b,v0.16b
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st1 {v2.16b},[x1]
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ret
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.size GFp_aes_hw_encrypt,.-GFp_aes_hw_encrypt
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.globl GFp_aes_hw_decrypt
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.hidden GFp_aes_hw_decrypt
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.type GFp_aes_hw_decrypt,%function
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.align 5
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GFp_aes_hw_decrypt:
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AARCH64_VALID_CALL_TARGET
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ldr w3,[x2,#240]
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ld1 {v0.4s},[x2],#16
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ld1 {v2.16b},[x0]
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sub w3,w3,#2
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ld1 {v1.4s},[x2],#16
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.Loop_dec:
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aesd v2.16b,v0.16b
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aesimc v2.16b,v2.16b
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ld1 {v0.4s},[x2],#16
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subs w3,w3,#2
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aesd v2.16b,v1.16b
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aesimc v2.16b,v2.16b
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ld1 {v1.4s},[x2],#16
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b.gt .Loop_dec
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aesd v2.16b,v0.16b
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aesimc v2.16b,v2.16b
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ld1 {v0.4s},[x2]
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aesd v2.16b,v1.16b
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eor v2.16b,v2.16b,v0.16b
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st1 {v2.16b},[x1]
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ret
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.size GFp_aes_hw_decrypt,.-GFp_aes_hw_decrypt
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.globl GFp_aes_hw_ctr32_encrypt_blocks
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.hidden GFp_aes_hw_ctr32_encrypt_blocks
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.type GFp_aes_hw_ctr32_encrypt_blocks,%function
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.align 5
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GFp_aes_hw_ctr32_encrypt_blocks:
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// Armv8.3-A PAuth: even though x30 is pushed to stack it is not popped later.
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AARCH64_VALID_CALL_TARGET
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stp x29,x30,[sp,#-16]!
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add x29,sp,#0
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ldr w5,[x3,#240]
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ldr w8, [x4, #12]
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ld1 {v0.4s},[x4]
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ld1 {v16.4s,v17.4s},[x3] // load key schedule...
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sub w5,w5,#4
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mov x12,#16
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cmp x2,#2
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add x7,x3,x5,lsl#4 // pointer to last 5 round keys
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sub w5,w5,#2
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ld1 {v20.4s,v21.4s},[x7],#32
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ld1 {v22.4s,v23.4s},[x7],#32
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ld1 {v7.4s},[x7]
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add x7,x3,#32
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mov w6,w5
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csel x12,xzr,x12,lo
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// ARM Cortex-A57 and Cortex-A72 cores running in 32-bit mode are
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// affected by silicon errata #1742098 [0] and #1655431 [1],
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// respectively, where the second instruction of an aese/aesmc
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// instruction pair may execute twice if an interrupt is taken right
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// after the first instruction consumes an input register of which a
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// single 32-bit lane has been updated the last time it was modified.
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//
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// This function uses a counter in one 32-bit lane. The vmov lines
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// could write to v1.16b and v18.16b directly, but that trips this bugs.
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// We write to v6.16b and copy to the final register as a workaround.
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//
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// [0] ARM-EPM-049219 v23 Cortex-A57 MPCore Software Developers Errata Notice
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// [1] ARM-EPM-012079 v11.0 Cortex-A72 MPCore Software Developers Errata Notice
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#ifndef __ARMEB__
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rev w8, w8
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#endif
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add w10, w8, #1
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orr v6.16b,v0.16b,v0.16b
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rev w10, w10
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mov v6.s[3],w10
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add w8, w8, #2
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orr v1.16b,v6.16b,v6.16b
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b.ls .Lctr32_tail
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rev w12, w8
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mov v6.s[3],w12
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sub x2,x2,#3 // bias
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orr v18.16b,v6.16b,v6.16b
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b .Loop3x_ctr32
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.align 4
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.Loop3x_ctr32:
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aese v0.16b,v16.16b
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aesmc v0.16b,v0.16b
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aese v1.16b,v16.16b
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aesmc v1.16b,v1.16b
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aese v18.16b,v16.16b
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aesmc v18.16b,v18.16b
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ld1 {v16.4s},[x7],#16
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subs w6,w6,#2
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aese v0.16b,v17.16b
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aesmc v0.16b,v0.16b
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aese v1.16b,v17.16b
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aesmc v1.16b,v1.16b
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aese v18.16b,v17.16b
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aesmc v18.16b,v18.16b
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ld1 {v17.4s},[x7],#16
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b.gt .Loop3x_ctr32
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aese v0.16b,v16.16b
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aesmc v4.16b,v0.16b
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aese v1.16b,v16.16b
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aesmc v5.16b,v1.16b
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ld1 {v2.16b},[x0],#16
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add w9,w8,#1
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aese v18.16b,v16.16b
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aesmc v18.16b,v18.16b
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ld1 {v3.16b},[x0],#16
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rev w9,w9
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aese v4.16b,v17.16b
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aesmc v4.16b,v4.16b
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aese v5.16b,v17.16b
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aesmc v5.16b,v5.16b
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ld1 {v19.16b},[x0],#16
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mov x7,x3
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aese v18.16b,v17.16b
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aesmc v17.16b,v18.16b
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aese v4.16b,v20.16b
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aesmc v4.16b,v4.16b
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aese v5.16b,v20.16b
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aesmc v5.16b,v5.16b
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eor v2.16b,v2.16b,v7.16b
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add w10,w8,#2
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|
aese v17.16b,v20.16b
|
||
|
|
aesmc v17.16b,v17.16b
|
||
|
|
eor v3.16b,v3.16b,v7.16b
|
||
|
|
add w8,w8,#3
|
||
|
|
aese v4.16b,v21.16b
|
||
|
|
aesmc v4.16b,v4.16b
|
||
|
|
aese v5.16b,v21.16b
|
||
|
|
aesmc v5.16b,v5.16b
|
||
|
|
// Note the logic to update v0.16b, v1.16b, and v1.16b is written to work
|
||
|
|
// around a bug in ARM Cortex-A57 and Cortex-A72 cores running in
|
||
|
|
// 32-bit mode. See the comment above.
|
||
|
|
eor v19.16b,v19.16b,v7.16b
|
||
|
|
mov v6.s[3], w9
|
||
|
|
aese v17.16b,v21.16b
|
||
|
|
aesmc v17.16b,v17.16b
|
||
|
|
orr v0.16b,v6.16b,v6.16b
|
||
|
|
rev w10,w10
|
||
|
|
aese v4.16b,v22.16b
|
||
|
|
aesmc v4.16b,v4.16b
|
||
|
|
mov v6.s[3], w10
|
||
|
|
rev w12,w8
|
||
|
|
aese v5.16b,v22.16b
|
||
|
|
aesmc v5.16b,v5.16b
|
||
|
|
orr v1.16b,v6.16b,v6.16b
|
||
|
|
mov v6.s[3], w12
|
||
|
|
aese v17.16b,v22.16b
|
||
|
|
aesmc v17.16b,v17.16b
|
||
|
|
orr v18.16b,v6.16b,v6.16b
|
||
|
|
subs x2,x2,#3
|
||
|
|
aese v4.16b,v23.16b
|
||
|
|
aese v5.16b,v23.16b
|
||
|
|
aese v17.16b,v23.16b
|
||
|
|
|
||
|
|
eor v2.16b,v2.16b,v4.16b
|
||
|
|
ld1 {v16.4s},[x7],#16 // re-pre-load rndkey[0]
|
||
|
|
st1 {v2.16b},[x1],#16
|
||
|
|
eor v3.16b,v3.16b,v5.16b
|
||
|
|
mov w6,w5
|
||
|
|
st1 {v3.16b},[x1],#16
|
||
|
|
eor v19.16b,v19.16b,v17.16b
|
||
|
|
ld1 {v17.4s},[x7],#16 // re-pre-load rndkey[1]
|
||
|
|
st1 {v19.16b},[x1],#16
|
||
|
|
b.hs .Loop3x_ctr32
|
||
|
|
|
||
|
|
adds x2,x2,#3
|
||
|
|
b.eq .Lctr32_done
|
||
|
|
cmp x2,#1
|
||
|
|
mov x12,#16
|
||
|
|
csel x12,xzr,x12,eq
|
||
|
|
|
||
|
|
.Lctr32_tail:
|
||
|
|
aese v0.16b,v16.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v16.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
ld1 {v16.4s},[x7],#16
|
||
|
|
subs w6,w6,#2
|
||
|
|
aese v0.16b,v17.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v17.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
ld1 {v17.4s},[x7],#16
|
||
|
|
b.gt .Lctr32_tail
|
||
|
|
|
||
|
|
aese v0.16b,v16.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v16.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
aese v0.16b,v17.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v17.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
ld1 {v2.16b},[x0],x12
|
||
|
|
aese v0.16b,v20.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v20.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
ld1 {v3.16b},[x0]
|
||
|
|
aese v0.16b,v21.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v21.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
eor v2.16b,v2.16b,v7.16b
|
||
|
|
aese v0.16b,v22.16b
|
||
|
|
aesmc v0.16b,v0.16b
|
||
|
|
aese v1.16b,v22.16b
|
||
|
|
aesmc v1.16b,v1.16b
|
||
|
|
eor v3.16b,v3.16b,v7.16b
|
||
|
|
aese v0.16b,v23.16b
|
||
|
|
aese v1.16b,v23.16b
|
||
|
|
|
||
|
|
cmp x2,#1
|
||
|
|
eor v2.16b,v2.16b,v0.16b
|
||
|
|
eor v3.16b,v3.16b,v1.16b
|
||
|
|
st1 {v2.16b},[x1],#16
|
||
|
|
b.eq .Lctr32_done
|
||
|
|
st1 {v3.16b},[x1]
|
||
|
|
|
||
|
|
.Lctr32_done:
|
||
|
|
ldr x29,[sp],#16
|
||
|
|
ret
|
||
|
|
.size GFp_aes_hw_ctr32_encrypt_blocks,.-GFp_aes_hw_ctr32_encrypt_blocks
|
||
|
|
#endif
|
||
|
|
#endif
|
||
|
|
#endif // !OPENSSL_NO_ASM
|
||
|
|
.section .note.GNU-stack,"",%progbits
|