ExternalVendorCode/AFLplusplus
1
0
Fork 0
mirror of https://github.com/AFLplusplus/AFLplusplus.git synced 2025-06-14 02:58:08 +00:00
Code Issues Packages Projects Releases Wiki Activity

solve typing error on QEMU with host arch i386

Browse Source
This commit is contained in:
Andrea Fioraldi
2019-12-15 14:17:54 +01:00
parent d40b670388
commit 6bf9855342
2 changed files with 17 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
qemu_mode/patches/afl-qemu-common.h
View File

@ -80,7 +80,7 @@ void afl_persistent_loop();
void tcg_gen_afl_call0(void *func); void tcg_gen_afl_call0(void *func);
void tcg_gen_afl_compcov_log_call(void *func, target_ulong cur_loc, void tcg_gen_afl_compcov_log_call(void *func, target_ulong cur_loc,
TCGv_i64 arg1, TCGv_i64 arg2); TCGv arg1, TCGv arg2);
void tcg_gen_afl_maybe_log_call(target_ulong cur_loc); void tcg_gen_afl_maybe_log_call(target_ulong cur_loc);

20
qemu_mode/patches/afl-qemu-tcg-inl.h
View File

@ -42,10 +42,15 @@ void tcg_gen_afl_maybe_log_call(target_ulong cur_loc) {
unsigned sizemask, flags; unsigned sizemask, flags;
TCGOp * op; TCGOp * op;
#if TARGET_LONG_BITS == 64
TCGTemp *arg = tcgv_i64_temp(tcg_const_tl(cur_loc)); TCGTemp *arg = tcgv_i64_temp(tcg_const_tl(cur_loc));
sizemask = dh_sizemask(void, 0) | dh_sizemask(i64, 1);
#else
TCGTemp *arg = tcgv_i32_temp(tcg_const_tl(cur_loc));
sizemask = dh_sizemask(void, 0) | dh_sizemask(i32, 1);
#endif
flags = 0; flags = 0;
sizemask = dh_sizemask(void, 0) | dh_sizemask(i64, 1);
#if defined(__sparc__) && !defined(__arch64__) && \ #if defined(__sparc__) && !defined(__arch64__) && \
!defined(CONFIG_TCG_INTERPRETER) !defined(CONFIG_TCG_INTERPRETER)
@ -372,19 +377,26 @@ void tcg_gen_afl_call0(void *func) {
} }
void tcg_gen_afl_compcov_log_call(void *func, target_ulong cur_loc, void tcg_gen_afl_compcov_log_call(void *func, target_ulong cur_loc,
TCGv_i64 arg1, TCGv_i64 arg2) { TCGv arg1, TCGv arg2) {
int i, real_args, nb_rets, pi; int i, real_args, nb_rets, pi;
unsigned sizemask, flags; unsigned sizemask, flags;
TCGOp * op; TCGOp * op;
const int nargs = 3; const int nargs = 3;
#if TARGET_LONG_BITS == 64
TCGTemp *args[3] = {tcgv_i64_temp(tcg_const_tl(cur_loc)), tcgv_i64_temp(arg1), TCGTemp *args[3] = {tcgv_i64_temp(tcg_const_tl(cur_loc)), tcgv_i64_temp(arg1),
tcgv_i64_temp(arg2)}; tcgv_i64_temp(arg2)};
flags = 0;
sizemask = dh_sizemask(void, 0) | dh_sizemask(i64, 1) | dh_sizemask(i64, 2) | sizemask = dh_sizemask(void, 0) | dh_sizemask(i64, 1) | dh_sizemask(i64, 2) |
dh_sizemask(i64, 3); dh_sizemask(i64, 3);
#else
TCGTemp *args[3] = {tcgv_i32_temp(tcg_const_tl(cur_loc)), tcgv_i32_temp(arg1),
tcgv_i32_temp(arg2)};
sizemask = dh_sizemask(void, 0) | dh_sizemask(i32, 1) | dh_sizemask(i32, 2) |
dh_sizemask(i32, 3);
#endif
flags = 0;
#if defined(__sparc__) && !defined(__arch64__) && \ #if defined(__sparc__) && !defined(__arch64__) && \
!defined(CONFIG_TCG_INTERPRETER) !defined(CONFIG_TCG_INTERPRETER)